1. Field of the Invention
The present invention is related to a method of manufacturing a liquid crystal device, and more particularly to a method of manufacturing a FFS(fringe field switching) mode-liquid crystal display device driving with fringe field.
2. Description of the Related Art
A FFS mode-liquid crystal display device is suggested for improving aperture ratio and transmittance as illustrated in U.S. Ser. No. 09/087,422. In this FFS mode-liquid crystal display device, counter and pixel electrodes are formed of a transparent conductor. Furthermore, the space between the counter and pixel electrodes is narrow, so that a fringe field is formed therebetween in a presence of electric field, thereby driving all liquid crystal molecules existing on the electrodes.
FIG. 1 is a simplified plan view of a conventional unit pixel and portions of adjacent pixel regions surrounding it in the liquid crystal display.
Referring to FIG. 1, the liquid crystal display includes a plurality of gate bus lines 13 arranged in parallel with each other on substrate in a first direction, and a plurality of data bus lines 19 arranged in parallel with each other on the substrate 10 in a second direction normal to the first direction. The plurality of gate bus lines 13 and the plurality of data bus lines 19 are arranged in a matrix configuration, to thereby define a plurality of pixel regions each bounded by a pair of gate bus lines 13 and a pair of data bus lines 19. The plurality of gate bus lines 13 and the plurality of data bus lines 19 are insulated from each other with gate insulating layer(not shown) intervening between the gate bus lines 13 and the data bus lines 19. A counter electrode 11 is formed as a rectangular frame structure within a respective pixel region and is disposed on a surface of the substrate altogether with the gate bus lines 13.
A pixel electrode 18 is arranged on a surface of the counter electrode 11 with the gate insulating layer(not shown) intervening therebetween.
FIG. 2 to FIG. 4 are cross sectional views for describing a method of manufacturing a FFS mode-liquid crystal display device according to the prior art. Here, FIG. 2 is a cross sectional view taken along the line A-B of FIG. 1, FIG. 3 is a cross sectional view taken along the line C-D of FIG. 1, and FIG. 4 is a cross sectional view of a pad portion.
Referring to FIG. 2 and FIG. 3, a first ITO(indium tin oxide) layer is deposited on a transparent insulating substrate 10 by sputtering using Ar gas and/or O2 gas and etched using a first mask, thereby forming a counter electrode 11 in the shape of comb. An insulating layer 12 as a protection layer is then formed on the substrate formed the counter electrode 11 and a first opaque metal layer is formed thereon by sputtering. Next, the first opaque metal layer is etched using a second mask to form a gate bus line 13 and a common electrode line (not shown). Here, the common electrode line is in contact with the counter electrode 11, as not shown in the drawing.
Thereafter, a gate insulating layer 14, an amorphous silicon layer and a silicon nitride layer are sequentially formed on the substrate formed the gate bus line 13 and the common electrode line. The silicon nitride layer is then etched using a third mask to form an etch stopper 15. Next, a doped amorphous silicon layer is deposited on the etch stopper 15 and the amorphous silicon layer by PECVD(Plasma Enhanced Chemical Vapor Deposition). The doped amorphous silicon layer and the amorphous silicon layer are then etched using a fourth mask to form a channel layer 16 and an ohmic layer 17. A second ITO layer is then deposited on the substrate formed the channel layer 16 and the ohmic layer 17 by sputtering and etched, thereby forming a pixel electrode 18 in the shape of comb between the comb of the counter electrode 11.
As shown in FIG. 4, the gate insulating layer 14 is etched using a sixth mask to open a pad portion 13a of the gate bus line 13. A second opaque metal layer is then deposited on the substrate opened the pad portion 13a of the gate bus line 13 by sputtering and etched using a seventh mask, thereby forming source/drain 19a and 19b and a data bus line 19. At this time, the ohmic layer 17 existing on the etch stopper 15 is removed and the opened pad portion 13a is in contact with the data bus line 19. Thereafter, a passivation layer 20 is deposited on the substrate formed the source/drain 19a and 19b and a data bus line 19. Preferably, the passivation layer 20 is formed of a silicon nitride layer. The passivation layer 20 is then etched so as to expose the data bus line 19.
However, as described above, eight masks are required for manufacturing the liquid crystal display device, so that process is complicated and process time is long. As a result, cost is increases and yield decreases.
It is therefore an object of the present invention to provide a method of manufacturing a fringe field switching mode-liquid crystal display device which can simplify process by reducing mask number, for solving the problems in the conventional art.
To accomplish this above object, according to the present invention, a method of manufacturing a liquid crystal display device driving with fringe field between counter and pixel electrodes, includes the steps of: depositing a first transparent conductive layer on a transparent insulating substrate and etching the first transparent conductive layer, thereby forming a counter electrode; forming a first insulating layer as a protection layer on the substrate formed the counter electrode; depositing a first metal layer on the first insulating layer and etching the first metal layer, thereby forming a gate bus line and a common electrode line, the common electrode line being in contact with the counter electrode; forming a gate insulating layer, an amorphous silicon layer and a second insulating layer on the substrate formed the gate bus line and the common electrode line; etching the second insulating layer to form an etch stopper; forming a doped amorphous silicon layer and a second metal layer on the substrate formed the etch stopper; etching the second metal layer to form source/drain and a data bus line; etching the doped amorphous silicon layer and the amorphous silicon layer using the source/drain as a mask to form an ohmic layer and a channel layer; forming a passivation layer on the substrate formed the ohmic layer and the channel layer; etching the passivation layer to open a pad portion of the gate bus line, a portion of the data bus line and the source; and depositing a second transparent conductive layer on the passivation and etching the second transparent conductive layer, thereby forming a pixel electrode, the pixel electrode being in contact with the opened source, the data bus line, and the pad portion of the gate bus line.
Additional object, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.